Issued Patents 2019
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10482984 | Ramp down sensing between program voltage and verify voltage in memory device | Xiang Yang, Deepanshu Dutta | 2019-11-19 |
| 10482985 | Dynamic erase loop dependent bias voltage | Xiang Yang, Deepanshu Dutta | 2019-11-19 |
| 10468111 | Asymmetric voltage ramp rate control | Xiang Yang, Deepanshu Dutta | 2019-11-05 |
| 10381083 | Bit line control that reduces select gate transistor disturb in erase operations | Xiang Yang, Kun-Huan Shih, Matthias Baenninger, Dengtao Zhao, Deepanshu Dutta | 2019-08-13 |
| 10229744 | First read countermeasures in memory | Deepanshu Dutta, Idan Alrod, Amul Desai, Jun Wan, Ken Cheong Cheah +1 more | 2019-03-12 |