Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10482984 | Ramp down sensing between program voltage and verify voltage in memory device | Xiang Yang, Huai-Yuan Tseng | 2019-11-19 |
| 10482985 | Dynamic erase loop dependent bias voltage | Xiang Yang, Huai-Yuan Tseng | 2019-11-19 |
| 10467134 | Dynamic anneal characteristics for annealing non-volatile memory | Navneeth Kankani, Linh Tien Truong, Sarath Puthenthermadam | 2019-11-05 |
| 10468111 | Asymmetric voltage ramp rate control | Xiang Yang, Huai-Yuan Tseng | 2019-11-05 |
| 10381083 | Bit line control that reduces select gate transistor disturb in erase operations | Xiang Yang, Kun-Huan Shih, Matthias Baenninger, Huai-Yuan Tseng, Dengtao Zhao | 2019-08-13 |
| 10229744 | First read countermeasures in memory | Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheong Cheah +1 more | 2019-03-12 |
| 10217520 | Pulsed control line biasing in memory | Muhammad Masuduzzaman, Jong Hak Yuh | 2019-02-26 |