Issued Patents 2019
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521113 | Memory system architecture | Suhas, Chaohong Hu | 2019-12-31 |
| 10515006 | Pseudo main memory system | Krishna T. Malladi, Jongmin Gim | 2019-12-24 |
| 10504572 | Methods for addressing high capacity SDRAM-like memory without increasing pin cost | Mu-Tien Chang, Dimin Niu, Sun-Young Lim, Indong Kim, Jangseok Choi | 2019-12-10 |
| 10496543 | Virtual bucket multiple hash tables for efficient memory in-line deduplication application | Frederic Sala, Chaohong Hu, Dimin Niu, Mu-Tien Chang | 2019-12-03 |
| 10489288 | Algorithm methodologies for efficient compaction of overprovisioned memory systems | Krishna T. Malladi | 2019-11-26 |
| 10474600 | Heterogeneous accelerator for highly efficient learning systems | Krishna T. Malladi | 2019-11-12 |
| 10437483 | Computing system with communication mechanism and method of operation thereof | Chaohong Hu, Liang Yin | 2019-10-08 |
| 10437785 | Method and apparatus for maximized dedupable memory | Dongyan Jiang, Qiang Peng | 2019-10-08 |
| 10437482 | Coordinated near-far memory controller for process-in-HBM | Mu-Tien Chang, Dimin Niu | 2019-10-08 |
| 10394648 | Method to deliver in-DRAM ECC information through DDR bus | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2019-08-27 |
| 10394719 | Refresh aware replacement policy for volatile memory cache | Mu-Tien Chang, Dimin Niu | 2019-08-27 |
| 10379939 | Memory apparatus for in-chip error correction | Krishna T. Malladi | 2019-08-13 |
| 10372606 | System and method for integrating overprovisioned memory devices | Krishna T. Malladi, Jongmin Gim | 2019-08-06 |
| 10347306 | Self-optimized power management for DDR-compatible memory systems | Mu-Tien Chang, Dimin Niu, Craig Hanson, Sun-Young Lim, Indong Kim +1 more | 2019-07-09 |
| 10318434 | Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application | Frederic Sala, Chaohong Hu, Dimin Niu, Mu-Tien Chang | 2019-06-11 |
| 10282294 | Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter | Mu-Tien Chang, Dimin Niu | 2019-05-07 |
| 10282436 | Memory apparatus for in-place regular expression search | Krishna T. Malladi | 2019-05-07 |
| 10268413 | Overflow region memory management | Dongyan Jiang, Changhui Lin, Krishna T. Malladi, Jongmin Gim | 2019-04-23 |
| 10268607 | Memory module threading with staggered data transfers | Frederick A. Ware | 2019-04-23 |
| 10268541 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2019-04-23 |
| 10261897 | Tail latency aware foreground garbage collection algorithm | Jongmin Gim | 2019-04-16 |
| 10242728 | DPU architecture | Shaungchen Li, Dimin Niu, Krishna T. Malladi | 2019-03-26 |
| 10223252 | Hybrid DRAM array including dissimilar memory cells | Mu-Tien Chang, Dimin Niu | 2019-03-05 |
| 10180808 | Software stack and programming for DPU operations | Shaungchen Li, Dimin Niu, Krishna T. Malladi | 2019-01-15 |
| 10180906 | HBM with in-memory cache manager | Tyler Stocksdale, Mu-Tien Chang | 2019-01-15 |