Issued Patents 2019
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10482943 | Systems and methods for improved error correction in a refreshable memory | Yanru Li | 2019-11-19 |
| 10394724 | Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns | Jungwon Suh, Haw-Jing Lo | 2019-08-27 |
| 10387333 | Non-volatile random access memory with gated security access | Yanru Li | 2019-08-20 |
| 10387242 | Dynamic link error protection in memory systems | Jungwon Suh, Alain Artieri, Deepti Vijayalakshmi Sriramagiri | 2019-08-20 |
| 10359803 | System memory latency compensation | Richard Alan Stewart | 2019-07-23 |
| 10338837 | Dynamic mapping of applications on NVRAM/DRAM hybrid memory | Subrato Kumar De, Yanru Li, Bohuslav Rychlik, Richard Alan Stewart | 2019-07-02 |
| 10332582 | Partial refresh technique to save memory refresh power | Jungwon Suh, Yanru Li, Michael Hawjing Lo | 2019-06-25 |
| 10310757 | Systems and methods for memory power saving via kernel steering to memory balloons | Yanru Li, Larry Bassel, Thomas Zeng | 2019-06-04 |
| 10296069 | Bandwidth-monitored frequency hopping within a selected DRAM operating point | Richard Alan Stewart | 2019-05-21 |
| 10224081 | Dynamic random access memory (DRAM) backchannel communication systems and methods | David Ian West, Michael Brunolli, Vaishnav Srinivas | 2019-03-05 |
| 10222853 | Power saving techniques for memory systems by consolidating data in data lanes of a memory bus | Jungwon Suh, Michael Hawjing Lo | 2019-03-05 |
| 10185515 | Unified memory controller for heterogeneous memory on a multi-chip package | Hyunsuk Shin, Jung Pill Kim, Jungwon Suh | 2019-01-22 |