Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10503643 | Cache coherence with functional address apertures | Wesley James HOLLAND, Hao Liu, Andrew E. Turner | 2019-12-10 |
| 10386904 | Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks | Jason Edward Podaima, Christophe Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski +4 more | 2019-08-20 |
| 10338837 | Dynamic mapping of applications on NVRAM/DRAM hybrid memory | Subrato Kumar De, Dexter Tamio Chun, Yanru Li, Richard Alan Stewart | 2019-07-02 |
| 10339058 | Automatic cache coherency for page table data | Andrew E. Turner, Farrukh HIJAZ | 2019-07-02 |
| 10261910 | Cache line compaction of compressed data segments | Andrew E. Turner, George Patsilaras | 2019-04-16 |
| 10255181 | Dynamic input/output coherency | Andrew E. Turner | 2019-04-09 |
| 10248565 | Hybrid input/output coherent write | Andrew E. Turner | 2019-04-02 |