Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10486963 | Wafer-level package with enhanced performance | Merrill Albert Hatcher, Jr., Jonathan Hale Hammond, Jon Chadwick, Jan Edward Vandemeer | 2019-11-26 |
| 10492301 | Method for manufacturing an integrated circuit package | George Maxim, Dirk Robert Walter Leipold, Baker Scott | 2019-11-26 |
| 10490471 | Wafer-level packaging for enhanced performance | Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick | 2019-11-26 |
| 10486965 | Wafer-level package with enhanced performance | Jan Edward Vandemeer, Jonathan Hale Hammond | 2019-11-26 |
| 10468329 | Thermally enhanced semiconductor package having field effect transistors with back-gate feature | George Maxim, Dirk Robert Walter Leipold, Baker Scott | 2019-11-05 |
| 10366972 | Microelectronics package with self-aligned stacked-die assembly | George Maxim | 2019-07-30 |
| 10276495 | Backside semiconductor die trimming | George Maxim, Dirk Robert Walter Leipold, Baker Scott | 2019-04-30 |
| 10262915 | Thermally enhanced semiconductor package with thermal additive and process for making the same | George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley | 2019-04-16 |
| 10199301 | Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer | Dirk Robert Walter Leipold, George Maxim, Baker Scott | 2019-02-05 |