Issued Patents 2019
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510414 | 3D NAND memory Z-decoder | — | 2019-12-17 |
| 10497406 | Sequential memory operation without deactivating access line signals | Peter Feeley | 2019-12-03 |
| 10490292 | Apparatuses and methods to control body potential in 3D non-volatile memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu +2 more | 2019-11-26 |
| 10468423 | Memory device including multiple select lines and control lines having different vertical spacing | — | 2019-11-05 |
| 10453538 | Apparatus and methods including establishing a negative body potential in a memory cell | Mark Hawes, Toru Tanzawa, Jeremy Binfet | 2019-10-22 |
| 10381091 | Reduced voltage nonvolatile flash memory | — | 2019-08-13 |
| 10360980 | Sequential write and sequential write verify in memory device | — | 2019-07-23 |
| 10354730 | Multi-deck memory device with access line and data line segregation between decks and method of operation thereof | — | 2019-07-16 |
| 10340009 | Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor | — | 2019-07-02 |
| 10319729 | Methods and apparatuses with vertical strings of memory cells and support circuitry | Takehiro Hasegawa | 2019-06-11 |
| 10242746 | Shielded vertically stacked data line architecture for memory | — | 2019-03-26 |
| 10181341 | Memory device including current generator plate | — | 2019-01-15 |
| 10170187 | Apparatuses and methods using negative voltages in part of memory write read, and erase operations | — | 2019-01-01 |
| 10170196 | Apparatuses and methods to control body potential in 3D non-volatile memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu +2 more | 2019-01-01 |