KM

Kishore Kumar Muchherla

Micron: 24 patents #3 of 1,093Top 1%
Overall (2019): #1,343 of 560,194Top 1%
24
Patents 2019

Issued Patents 2019

Patent #TitleCo-InventorsDate
10521146 UFS based idle time garbage collection management Kulachet Tanpairoj, Jianmin Huang 2019-12-31
10510422 Memory devices with read level calibration Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Renato C. Padilla +3 more 2019-12-17
10509722 Memory device with dynamic cache management Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt +3 more 2019-12-17
10452282 Memory management Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Preston A. Thomson, Renato C. Padilla +1 more 2019-10-22
10446197 Optimized scan interval Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath K. Ratnam +1 more 2019-10-15
10430116 Correcting power loss in NAND memory devices Michael G. Miller, Harish Reddy Singidi, Sampath K. Ratnam, Renato C. Padilla, Gary F. Besinga +1 more 2019-10-01
10430262 Identifying asynchronous power loss Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga +4 more 2019-10-01
10418122 Threshold voltage margin analysis Sampath K. Ratnam, Abolfazl Rashwand 2019-09-17
10403378 Performing an operation on a memory cell of a memory system at a frequency based on temperature Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Peter Feeley, Renato C. Padilla +1 more 2019-09-03
10380018 Garbage collection Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla +2 more 2019-08-13
10365854 Tracking data temperatures of logical block addresses Peter Feeley, Ashutosh Malshe, Sampath K. Ratnam, Harish Reddy Singidi, Vamsi Pavan Rayaprolu 2019-07-30
10366763 Block read count voltage adjustment Harish Reddy Singidi, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath K. Ratnam, Gary F. Besinga +1 more 2019-07-30
10359933 Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods Ashutosh Malshe, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale +1 more 2019-07-23
10354732 NAND temperature data management Sampath K. Ratnam, Preston A. Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Feeley +1 more 2019-07-16
10347344 Read voltage calibration based on host IO operations Ashutosh Malshe, Harish Reddy Singidi, Peter Feeley, Sampath K. Ratnam, Kulachet Tanpairoj +1 more 2019-07-09
10340016 Methods of error-based read disturb mitigation and memory devices utilizing the same Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam +3 more 2019-07-02
10325668 Operation of mixed mode blocks Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott Anthony Stoller +3 more 2019-06-18
10318378 Redundant array of independent NAND for a three-dimensional memory array Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Sivagnanam Parthasarathy, Peter Feeley 2019-06-11
10303614 Memory having a static cache and a dynamic cache Christopher S. Hale, Sampath K. Ratnam 2019-05-28
10303535 Identifying asynchronous power loss Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga +4 more 2019-05-28
10283205 Preemptive idle time read scans Ashutosh Malshe, Harish Reddy Singidi, Michael G. Miller, Sampath K. Ratnam, John Zhang +1 more 2019-05-07
10248594 Programming interruption management Preston A. Thomson, Sampath K. Ratnam 2019-04-02
10223259 Memory device with dynamic storage mode control Yun Li, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale +2 more 2019-03-05
10199111 Memory devices with read level calibration Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Renato C. Padilla +3 more 2019-02-05