Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489312 | Stack access control for memory device | Seiji Narui, Homare Sato | 2019-11-26 |
| 10468386 | TSV redundancy and TSV test select scheme | Homare Sato, Akira Ide | 2019-11-05 |
| 10459871 | Switching reduction bus using data bit inversion with shield lines | Akinori Funahashi | 2019-10-29 |
| 10395748 | Shared error detection and correction memory | Tomoyuki Shibata, Hiroyuki Tanaka | 2019-08-27 |
| 10373657 | Semiconductor layered device with data bus | Chiaki Dono | 2019-08-06 |
| 10338997 | Apparatuses and methods for fixing a logic level of an internal signal line | Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya | 2019-07-02 |
| 10262704 | Apparatuses and methods for providing multiphase clock signals | Homare Sato, Chiaki Dono | 2019-04-16 |
| 10185652 | Stack access control for memory device | Seiji Narui, Homare Sato | 2019-01-22 |
| 10181347 | Semiconductor device, adjustment method thereof and data processing system | Naohisa Nishioka | 2019-01-15 |