Issued Patents 2019
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10455690 | Grid array pattern for crosstalk reduction | Ranjeeth Doppalapudi | 2019-10-22 |
| 10455691 | Grid array pattern for crosstalk reduction | — | 2019-10-22 |
| 10383213 | Placement of vias in printed circuit board circuits | Edward Chang, Ranjeeth Doppalapudi, Santosh Kumar Pappu | 2019-08-13 |
| 10365314 | Electrical signature fault detection | Ranjeeth Doppalapudi | 2019-07-30 |
| 10231325 | Placement of vias in printed circuit board circuits | Edward Chang, Ranjeeth Doppalapudi, Santosh Kumar Pappu | 2019-03-12 |