Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10475900 | Method for manufacturing a semiconductor device with a cobalt silicide film | Kai-Jiun Chang, Tsun-Min Cheng, Chih-Chieh Tsai, Jui-Min Lee, Yi-Wei Chen +1 more | 2019-11-12 |
| 10475662 | Method of forming semiconductor device | Feng-Yi Chang, Ying-Chih Lin, Jui-Min Lee, Gang-Yi Lin, Fu-Che Lee | 2019-11-12 |
| 10453677 | Method of forming oxide layer | Cheng-Hsu Huang, Jui-Min Lee, Ching-Hsiang Chang, Yi-Wei Chen, Shih-Fang Tzou | 2019-10-22 |
| 10340278 | Semiconductor memory device and manufacturing method thereof | Cheng-Hsu Huang, Jui-Min Lee, Yi-Wei Chen | 2019-07-02 |
| 10312080 | Method for forming amorphous silicon multuple layer structure | Mei-Ling Chen, Yi-Wei Chen, Ching-Hsiang Chang, Jui-Min Lee, Chia-Lung Chang +2 more | 2019-06-04 |
| 10276650 | Semiconductor memory device and manufacturing method thereof | Tzu-Chin Wu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen +6 more | 2019-04-30 |
| 10262895 | Method for forming semiconductor device | Mei-Ling Chen, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Ching-Hsiang Chang +2 more | 2019-04-16 |
| 10249706 | Semiconductor structure | Chia-Lung Chang, Po-Chun Chen, Yi-Wei Chen, Han-Yung Tsai, Tzu-Chin Wu +1 more | 2019-04-02 |
| 10224324 | Method for manufacturing semiconductor device having gate structure with reduced threshold voltage | Pi-Hsuan Lai | 2019-03-05 |
| 10186453 | Semiconductor structure and process thereof | Bin-Siang Tsai | 2019-01-22 |