Issued Patents 2019
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489069 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2019-11-26 |
| 10419035 | Use of multiple cyclic redundancy codes for optimized fail isolation | Steven R. Carlough, Gary A. Van Huben | 2019-09-17 |
| 10395698 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Stephen J. Powell, Gary A. Van Huben +1 more | 2019-08-27 |
| 10379748 | Predictive scheduler for memory rank switching | James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Craig R. Walters | 2019-08-13 |
| 10353606 | Partial data replay in a distributed memory buffer system | Susan M. Eickhoff, Steven R. Carlough, Stephen J. Powell, Jie Zheng, Gary A. Van Huben | 2019-07-16 |
| 10303545 | High efficiency redundant array of independent memory | Christian Jacobi, Barry M. Trager | 2019-05-28 |
| 10296417 | Reducing uncorrectable errors based on a history of correctable errors | Glenn D. Gilda | 2019-05-21 |
| 10175893 | Predictive scheduler for memory rank switching | James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Craig R. Walters | 2019-01-08 |