Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10516401 | Wobble reduction in an integer mode digital phase locked loop | Jayawardan Janardhanan, Henry Yao | 2019-12-24 |
| 10516402 | Corrupted clock detection circuit for a phase-locked loop | Arvind Krishna SRIDHAR, Jayawardan Janardhanan | 2019-12-24 |
| 10491222 | Switch between input reference clocks of different frequencies in a phase locked loop (PLL) without phase impact | Sinjeet Dhanvantray Parekh, Christopher Andrew Schell, Jayawardan Janardhanan | 2019-11-26 |