Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10516401 | Wobble reduction in an integer mode digital phase locked loop | Jayawardan Janardhanan, Eric Paul LINDGREN | 2019-12-24 |
| 10505554 | Digital phase-locked loop | Jayawardan Janardhanan, Christopher Andrew Schell, Raghu Ganesan | 2019-12-10 |
| 10496041 | Time-to-digital converter circuit | Sinjeet Dhanvantray Parekh | 2019-12-03 |