Issued Patents 2019
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10481915 | Split store data queue design for an out-of-order processor | Balaram Sinharoy | 2019-11-19 |
| 10417002 | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses | Balaram Sinharoy, Shih-Hsiung S. Tung | 2019-09-17 |
| 10394558 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Balaram Sinharoy | 2019-08-27 |
| 10324856 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Balaram Sinharoy, Shih-Hsiung S. Tung | 2019-06-18 |
| 10310988 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Balaram Sinharoy, Shih-Hsiung S. Tung | 2019-06-04 |