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Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption |
Yevgeniy M. Astigeyevich, Dmitry M. Maslennikov, Marat Zakirov, Pavel G. Matveyev, Andrey Rodchenko +2 more |
2019-10-01 |
| 10241789 |
Method to do control speculation on loads in a high performance strand-based loop accelerator |
Alexander Y. Ostanevich, Jayesh Iyer, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more |
2019-03-26 |
| 10241794 |
Apparatus and methods to support counted loop exits in a multi-strand loop processor |
Jayesh Iyer, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more |
2019-03-26 |
| 10241801 |
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator |
Jayesh Iyer, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more |
2019-03-26 |
| 10235171 |
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor |
Alexander Y. Ostanevich, Jayesh Iyer, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich +3 more |
2019-03-19 |