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Memory device including concurrent suspend states for different operations |
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Pseudo single pass NAND memory programming |
Xin Guo, David B. Carlton, Purval S. Sule |
2019-10-15 |
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System and method for performing a concurrent multiple page read of a memory array |
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2019-10-08 |
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Techniques for non-volatile memory page retirement |
Feng Zhu, Xin Guo |
2019-10-08 |
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Concurrent copying of first and second subsets of pages from media such as SLC NAND to media such as QLC or MLC NAND for completion of copying of data |
Shankar Natarajan |
2019-10-01 |
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One check fail byte (CFBYTE) scheme |
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NAND flash thermal alerting |
Naveen Vittal Prabhu, Simon Ramage |
2019-06-25 |
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Block by deck operations for NAND memory |
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Xin Guo, Ali Khakifirooz, Pranav Kalavade, Sagar Upadhyay |
2019-04-30 |
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Data preservation and recovery in a memory component |
Shankar Natarajan, Wayne Tran |
2019-04-23 |
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Matthew Goldman, Wayne Tran, Sungho Park |
2019-04-23 |
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Method and apparatus for specifying read voltage offsets for a read command |
Xin Guo, Naveen Vittal Prabhu, Yu Du, Purval S. Sule |
2019-04-23 |
| 10242734 |
Resuming storage die programming after power loss |
Ali Khakifirooz, Rohit S. Shenoy, Pranav Kalavade, Yogesh B. Wakchaure |
2019-03-26 |
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Method and apparatus for avoiding bus contention after initialization failure |
Kristopher H. Gaewsky, Bharat Pathak |
2019-03-12 |
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Method and apparatus for dynamically determining start program voltages for a memory device |
Purval S. Sule, Shantanu R. Rajwade, Trupti Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky |
2019-03-05 |
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Methods and apparatus to perform erase-suspend operations in memory devices |
Yogesh B. Wakchaure, Camila Jaramillo, Trupti Bemalkhedkar |
2019-02-12 |
| 10175903 |
N plane to 2N plane interface in a solid state drive (SSD) architecture |
Xin Guo, Joel T Jorgensen |
2019-01-08 |
