Issued Patents 2019
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10388793 | Gate-all-around fin device | John B. Campi, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2019-08-20 |
| 10381484 | Gate-all-around fin device | John B. Campi, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2019-08-13 |
| 10381483 | Gate-all-around fin device | John B. Campi, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2019-08-13 |
| 10361293 | Vertical fin-type devices and methods | Tsung-Che Tsai, Alain Loiseau, Souvick Mitra, You Li, Mickey H. Yu | 2019-07-23 |
| 10359461 | Integrated circuit protection during high-current ESD testing | Shunhua T. Chang, James P. Di Sarro, Nathan Jack, Souvick Mitra | 2019-07-23 |
| 10347622 | Silicon-controlled rectifiers having a cathode coupled by a contact with a diode trigger | You Li, Manjunatha Prabu, Mujahid Muhammad, John B. Campi, Jr., Souvick Mitra | 2019-07-09 |
| 10297589 | Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode | Tom C. Lee, You Li, Rahul Mishra, Souvick Mitra, Andreas Scholze | 2019-05-21 |
| 10290626 | High voltage electrostatic discharge (ESD) bipolar integrated in a vertical field-effect transistor (VFET) technology and method for producing the same | You Li, Alain Loiseau, Tsung-Che Tsai, Mickey H. Yu, Souvick Mitra | 2019-05-14 |
| 10283959 | ESD state-controlled semiconductor-controlled rectifier | John B. Campi, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2019-05-07 |
| 10283374 | Structures, methods and applications for electrical pulse anneal processes | Michel J. Abou-Khalil, Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam +1 more | 2019-05-07 |
| 10224710 | Electrostatic discharge power clamp with fail-safe design | John A. Fifield, Junjun Li | 2019-03-05 |
| 10186860 | Electrostatic discharge device with fail-safe design | John A. Fifield, Junjun Li | 2019-01-22 |
| 10181463 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | James P. Di Sarro, Nathan Jack, Junjun Li, Souvick Mitra | 2019-01-15 |