Issued Patents 2019
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10191850 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan | 2019-01-29 |