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Neuromorphic event-driven neural computing architecture in a scalable neural network |
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2019-12-10 |
| 10454759 |
Yield tolerance in a neurosynaptic system |
Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more |
2019-10-22 |
| 10452540 |
Memory-mapped interface for message passing computing systems |
Filipp A. Akopyan, Andrew S. Cassidy, Michael Vincent DeBole, Paul A. Merolla, Dharmendra S. Modha +1 more |
2019-10-22 |
| 10410109 |
Peripheral device interconnections for neurosynaptic systems |
Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more |
2019-09-10 |
| 10331998 |
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network |
Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more |
2019-06-25 |
| 10282658 |
Hardware architecture for simulating a neural network of neurons |
Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha |
2019-05-07 |
| 10204118 |
Mapping neural dynamics of a neural model on to a coarsely grained look-up table |
Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha |
2019-02-12 |
| 10198692 |
Scalable neural hardware for the noisy-OR model of Bayesian networks |
Steven K. Esser, Paul A. Merolla, Dharmendra S. Modha |
2019-02-05 |
| 10176063 |
Faulty core recovery mechanisms for a three-dimensional network on a processor array |
Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Paul A. Merolla +1 more |
2019-01-08 |
| 10169700 |
Neuromorphic network comprising asynchronous routers and synchronous core circuits |
Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha |
2019-01-01 |
