Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490464 | Methods for assessing semiconductor structures | Igor Rapoport, Srikanth Kommu, Igor Peidous, Gang Wang | 2019-11-26 |
| 10483152 | High resistivity semiconductor-on-insulator wafer and a method of manufacturing | Igor Peidous, Lu Fei, Andrew M. Jones, Alex Usenko, Gang Wang +2 more | 2019-11-19 |
| 10475695 | High resistivity silicon-on-insulator substrate comprising an isolation region | Igor Peidous | 2019-11-12 |
| 10475696 | Method of manufacture of a semiconductor on insulator structure | Henry F. Erk, Sasha Kweskin, Mayank Bulsara | 2019-11-12 |
| 10468294 | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface | Igor Peidous, Andrew M. Jones, Srikanth Kommu, Gang Wang | 2019-11-05 |
| 10381261 | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | Igor Peidous, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez +2 more | 2019-08-13 |
| 10381260 | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | Igor Peidous, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez +2 more | 2019-08-13 |
| 10283402 | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress | Gang Wang, Shawn George Thomas, Igor Peidous | 2019-05-07 |
| 10269617 | High resistivity silicon-on-insulator substrate comprising an isolation region | Igor Peidous | 2019-04-23 |