Issued Patents 2019
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10402324 | Memory access for busy memory by receiving data from cache during said busy period and verifying said data utilizing cache hit bit or cache miss bit | Kevin T. Lim, Sheng Li, Parthasarathy Ranganathan | 2019-09-03 |