VR

Vincent Gregory Reynolds

CS Cadence Design Systems: 1 patents #113 of 394Top 30%
Overall (2019): #229,655 of 560,194Top 45%
1
Patents 2019

Issued Patents 2019

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
10325042 Debugging failures in X-propagation logic circuit simulation Amit Sharma, Amit Aggarwal, Amit Dua, Manu Chopra, Abhishek Raheja 2019-06-18