Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10389368 | Dual path phase-locked loop circuit | Fuyue Wang, Ling Chen, Jianyun Zhang, Eric Naviasky | 2019-08-20 |
| 10345845 | Fast settling bias circuit | Ling Chen, Fuyue Wang, Jianyun Zhang, Eric Naviasky | 2019-07-09 |
| 10193555 | Methods and devices for a memory interface receiver | Eric Naviasky | 2019-01-29 |