FW

Fuyue Wang

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
Overall (2019): #172,545 of 560,194Top 35%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10389368 Dual path phase-locked loop circuit Ling Chen, Thomas Evan Wilson, Jianyun Zhang, Eric Naviasky 2019-08-20
10345845 Fast settling bias circuit Ling Chen, Thomas Evan Wilson, Jianyun Zhang, Eric Naviasky 2019-07-09