SS

Sundararajan Shanmugam

CS Cadence Design Systems: 1 patents #113 of 394Top 30%
📍 San Jose, CA: #2,930 of 6,652 inventorsTop 45%
🗺 California: #27,528 of 67,890 inventorsTop 45%
Overall (2019): #256,530 of 560,194Top 50%
1
Patents 2019

Issued Patents 2019

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
10210301 System and method for implementing and validating star routing for power connections at chip level Ankur Chavhan, Devesh Jain, Behnam Farhat, Andrey Freidlin, Susan ZHANG 2019-02-19