PG

Praveen Ghanta

CS Cadence Design Systems: 3 patents #23 of 394Top 6%
📍 Cupertino, CA: #270 of 1,624 inventorsTop 20%
🗺 California: #9,221 of 67,890 inventorsTop 15%
Overall (2019): #73,135 of 560,194Top 15%
3
Patents 2019

Issued Patents 2019

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10430536 Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation Igor Keller, Mikhail Chetin 2019-10-01
10275554 Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design Mikhail Chetin, Igor Keller 2019-04-30
10185795 Systems and methods for statistical static timing analysis Igor Keller, Arun Kumar Mishra 2019-01-22