MC

Mikhail Chetin

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 San Jose, CA: #1,646 of 6,652 inventorsTop 25%
🗺 California: #14,923 of 67,890 inventorsTop 25%
Overall (2019): #140,118 of 560,194Top 30%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10430536 Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation Igor Keller, Praveen Ghanta 2019-10-01
10275554 Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design Igor Keller, Praveen Ghanta 2019-04-30