NK

Navneet Kaushik

CS Cadence Design Systems: 1 patents #113 of 394Top 30%
Overall (2019): #332,296 of 560,194Top 60%
1
Patents 2019

Issued Patents 2019

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
10192013 Test logic at register transfer level in an integrated circuit design Puneet Arora, Ankit Bandejia, Steven Lee Gregor 2019-01-29