MP

Mitchell G. Poplack

CS Cadence Design Systems: 5 patents #9 of 394Top 3%
📍 San Jose, CA: #547 of 6,652 inventorsTop 9%
🗺 California: #4,328 of 67,890 inventorsTop 7%
Overall (2019): #32,251 of 560,194Top 6%
5
Patents 2019

Issued Patents 2019

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
10509877 Systems and methods for reducing latency when transferring I/O between an emulator and target device Viktor Salitrennik, Gavin Zawalski 2019-12-17
10386909 Method and system to mitigate large power load steps due to intermittent execution in a computation system Yuhei Hayashi 2019-08-20
10324740 Enhanced control system for flexible programmable logic and synchronization Yuhei Hayashi 2019-06-18
10303230 Method and system to mitigate large power load steps due to intermittent execution in a computation system Yuhei Hayashi, Beshara Elmufdi, Hitesh Gannu 2019-05-28
10198538 Relocate targets to different domains in an emulator Barton L. Quayle, Sundar Rajan, Chuck Berghorn 2019-02-05