HG

Hitesh Gannu

CS Cadence Design Systems: 1 patents #113 of 394Top 30%
📍 San Jose, CA: #2,930 of 6,652 inventorsTop 45%
🗺 California: #27,528 of 67,890 inventorsTop 45%
Overall (2019): #446,549 of 560,194Top 80%
1
Patents 2019

Issued Patents 2019

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
10303230 Method and system to mitigate large power load steps due to intermittent execution in a computation system Mitchell G. Poplack, Yuhei Hayashi, Beshara Elmufdi 2019-05-28