KC

Krishna Vijaya Chakravadhanula

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 Vestal, NY: #9 of 38 inventorsTop 25%
🗺 New York: #2,767 of 13,137 inventorsTop 25%
Overall (2019): #149,129 of 560,194Top 30%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10331506 SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores Vivek Chickermane, Christos Papameletis, Brian Foutz 2019-06-25
10325048 Virtual directory navigation and debugging across multiple test configurations in the same session Sameer Chakravarthy Chillarige, Sonam Kathpalia, Mehakpreet Kaur, James Allen 2019-06-18