JK

Jagjot Kaur

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 Milpitas, CA: #124 of 588 inventorsTop 25%
🗺 California: #14,923 of 67,890 inventorsTop 25%
Overall (2019): #162,905 of 560,194Top 30%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10417363 Power and scan resource reduction in integrated circuit designs having shift registers Priyanka Dasgupta, Pratyush Aditya Kothamasu, Vivek Chickermane 2019-09-17
10234504 Optimizing core wrappers in an integrated circuit Subhasish Mukherjee, Vivek Chickermane, Susan Marie Genova 2019-03-19