AV

Avnish Varma

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 Noida, IN: #14 of 134 inventorsTop 15%
Overall (2019): #190,510 of 560,194Top 35%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10515174 Interface modeling for power analysis of an integrated circuit Rishabh, Xin Gu 2019-12-24
10387595 Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit Anshu Mani, Suketu Desai 2019-08-20