SD

Suketu Desai

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 Milpitas, CA: #124 of 588 inventorsTop 25%
🗺 California: #14,923 of 67,890 inventorsTop 25%
Overall (2019): #116,999 of 560,194Top 25%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10460055 Modeling of sequential circuit devices of multi-clock domain IC design for a transient vectorless power analysis Yuvaraj Gogoi, Bhuvnesh Kumar, Anshu Mani 2019-10-29
10387595 Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit Anshu Mani, Avnish Varma 2019-08-20