AB

Ajay Singh Bisht

AN Ansys: 1 patents #8 of 34Top 25%
CS Cadence Design Systems: 1 patents #113 of 394Top 30%
📍 San Jose, CA: #1,646 of 6,652 inventorsTop 25%
🗺 California: #14,923 of 67,890 inventorsTop 25%
Overall (2019): #195,910 of 560,194Top 35%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10417365 Systems and methods for reducing power consumption of latch-based circuits Allen Baker 2019-09-17
10248746 Method and apparatus for estimating ideal power of an integrated circuit design Jayanta Roy, Kamlesh Kumar Madheshiya, Kunwar Prashant 2019-04-02