Issued Patents 2018
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10134643 | Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow | Steven Lee Prins | 2018-11-20 |
| 10026837 | Embedded SiGe process for multi-threshold PMOS transistors | Deborah J. Riley | 2018-07-17 |
| 10008499 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote | 2018-06-26 |
| 9947765 | Dummy gate placement methodology to enhance integrated circuit performance | Shashank S. Ekbote, Gregory Charles Baldwin | 2018-04-17 |