Issued Patents 2018
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164096 | Semiconductor device and manufacturing method thereof | Kun-Mu Li, Ming-Hua Yu, Chan-Lon Yang | 2018-12-25 |
| 10158016 | MOS devices with non-uniform p-type impurity profile | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2018-12-18 |
| 10084089 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2018-09-25 |
| 10062781 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2018-08-28 |
| 10049936 | Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same | Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Ming-Hua Yu | 2018-08-14 |
| 10014411 | Modulating germanium percentage in MOS devices | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2018-07-03 |
| 9991364 | Transistor strain-inducing scheme | Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2018-06-05 |
| 9922975 | Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof | Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu | 2018-03-20 |
| 9911826 | Devices with strained source/drain structures | Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin | 2018-03-06 |
| 9905646 | V-shaped epitaxially formed semiconductor layer | Ming-Hua Yu, Chii-Horng Li | 2018-02-27 |