Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164076 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu | 2018-12-25 |
| 10163901 | Method and device for embedding flash memory and logic integration in FinFET technology | Pinghui Li, Su Yi Susan Yeow, Yiang Aun Nga, Danny Pak-Chum Shum, Eng Huat Toh | 2018-12-25 |
| 10134743 | Structure and method for statice random access memory device of vertical tunneling field effect transistor | Harry-Hak-Lay Chuang, Bao-Ru Young, Wei-Cheng Wu, Yi-Ren Chen | 2018-11-20 |
| 10109638 | Embedded non-volatile memory (NVM) on fully depleted silicon-on-insulator (FD-SOI) substrate | Pinghui Li, Danny Pak-Chum Shum, Fan Zhang, Yiang Aun Nga | 2018-10-23 |
| 10103253 | Structure and method for vertical tunneling field effect transistor with leveled source and drain | Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang | 2018-10-16 |
| 9978853 | Method of forming gate structure of a semiconductor device | Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen +4 more | 2018-05-22 |
| 9947528 | Structure and method for nFET with high k metal gate | Jin-Aun Ng, Chi-Wen Liu | 2018-04-17 |
| 9865510 | Device and methods for high-K and metal gate slacks | Po-Nien Chen, Bao-Ru Young, Harry-Hak-Lay Chuang, Jin-Aun Ng | 2018-01-09 |
| 9865716 | System and method for a vertical tunneling field-effect transistor cell | Harry-Hak-Lay Chuang | 2018-01-09 |