Issued Patents 2018
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157676 | Dynamic tuning of first read countermeasures | Yingda Dong, Jiahui Yuan, Charles See Yeung Kwong | 2018-12-18 |
| 10128257 | Select transistors with tight threshold voltage in 3D memory | Jayavel Pachamuthu, Yingda Dong | 2018-11-13 |
| 10121552 | Reducing charge loss in data memory cell adjacent to dummy memory cell | Ashish Baraskar, Yingda Dong, Ching-Huang Lu, Nan Lu, Hong-Yan Chen | 2018-11-06 |
| 10068657 | Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels | Xuehong Yu, Yingda Dong | 2018-09-04 |
| 10020314 | Forming memory cell film in stack opening | Ashish Baraskar, Yanli Zhang, Ching-Huang Lu, Yingda Dong | 2018-07-10 |
| 10008277 | Block health monitoring using threshold voltage of dummy memory cells | Xuehong Yu, Yingda Dong, Nian Niles Yang | 2018-06-26 |
| 9984760 | Suppressing disturb of select gate transistors during erase in memory | Zhengyi Zhang, Yingda Dong | 2018-05-29 |
| 9952944 | First read solution for memory | Idan Alrod, Eran Sharon, Alon Eyal, Evgeny Mekhanik | 2018-04-24 |
| 9941293 | Select transistors with tight threshold voltage in 3D memory | Jayavel Pachamuthu, Yingda Dong | 2018-04-10 |
| 9911500 | Dummy voltage to reduce first read effect in memory | Pao-Ling Koh, Jiahui Yuan, Charles See Yeung Kwong, Yingda Dong | 2018-03-06 |
| 9859298 | Amorphous silicon layer in memory device which reduces neighboring word line interference | Jayavel Pachamuthu, Yingda Dong | 2018-01-02 |