Issued Patents 2018
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10147222 | Multi-pass rendering in a screen space pipeline | Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Jeffrey A. Bolz, Yury Uralsky, Jonah M. Alben | 2018-12-04 |
| 10120187 | Sub-frame scanout for latency reduction in virtual reality applications | Craig M. Wittenbrink | 2018-11-06 |
| 10083036 | Techniques for managing graphics processing resources in a tile-based architecture | Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Andrei Khodakovsky, Jeffrey A. Bolz | 2018-09-25 |
| 10078911 | System, method, and computer program product for executing processes involving at least one primitive in a graphics processor, utilizing a data structure | Yury Uralsky, Tyson J. Bergland, Eric B. Lum, Jerome F. Duluk, Jr., Henry Packard Moreton | 2018-09-18 |
| 10068366 | Stereo multi-projection implemented using a graphics processing pipeline | Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff | 2018-09-04 |
| 10055806 | Techniques for maintaining atomicity and ordering for pixel shader operations | Eric B. Lum, Dale L. Kirkland, Jack Choquette, Patrick R. Brown, Yury Uralsky +1 more | 2018-08-21 |
| 10032245 | Techniques for maintaining atomicity and ordering for pixel shader operations | Eric B. Lum, Dale L. Kirkland, Jack Choquette, Patrick R. Brown, Yury Uralsky +1 more | 2018-07-24 |
| 10032243 | Distributed tiled caching | Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner | 2018-07-24 |
| 10032242 | Managing deferred contexts in a cache tiling architecture | Jeffrey A. Bolz, Amanpreet Grewal, Matthew Vernon Johnson, Andrei Khodakovsky | 2018-07-24 |
| 10019776 | Techniques for maintaining atomicity and ordering for pixel shader operations | Eric B. Lum, Dale L. Kirkland, Jack Choquette, Patrick R. Brown, Yury Uralsky +1 more | 2018-07-10 |
| 9952868 | Two-pass cache tile processing for visibility testing in a tile-based architecture | Jerome F. Duluk, Jr. | 2018-04-24 |