Issued Patents 2018
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10110499 | QoS in a system with end-to-end flow control and QoS aware buffer allocation | — | 2018-10-23 |
| 10084725 | Extracting features from a NoC for machine learning construction | Pier Giorgio Raponi, Nishant Rao | 2018-09-25 |
| 10084692 | Streaming bridge design with host interfaces and network on chip (NoC) layers | Rajesh Chopra | 2018-09-25 |
| 10074053 | Clock gating for system-on-chip elements | Sandip Das, Poonacha Kongetira | 2018-09-11 |
| 10063496 | Buffer sizing of a NoC through machine learning | Eric Norige, Nishant Rao | 2018-08-28 |
| 10050843 | Generation of network-on-chip layout based on user specified topological constraints | Pier Giorgio Raponi, Eric Norige | 2018-08-14 |
| 10042404 | Automatic generation of power management sequence in a SoC or NoC | Anup Gangwar, Vishnu Mohan Pusuluri, Poonacha Kongetira | 2018-08-07 |
| 10027433 | Multiple clock domains in NoC | Joji Philip, Joseph B. Rowlands | 2018-07-17 |
| 9928204 | Transaction expansion for NoC simulation and NoC design | Eric Norige | 2018-03-27 |
| 9864728 | Automatic generation of physically aware aggregation/distribution networks | Eric Norige | 2018-01-09 |
| 9860197 | Automatic buffer sizing for optimal network-on-chip design | — | 2018-01-02 |