Issued Patents 2018
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10063496 | Buffer sizing of a NoC through machine learning | Nishant Rao, Sailesh Kumar | 2018-08-28 |
| 10050843 | Generation of network-on-chip layout based on user specified topological constraints | Pier Giorgio Raponi, Sailesh Kumar | 2018-08-14 |
| 9928204 | Transaction expansion for NoC simulation and NoC design | Sailesh Kumar | 2018-03-27 |
| 9864728 | Automatic generation of physically aware aggregation/distribution networks | Sailesh Kumar | 2018-01-09 |