BS

Brad Sharpe-Geisler

LS Lattice Semiconductor: 2 patents #10 of 76Top 15%
📍 San Jose, CA: #1,359 of 5,991 inventorsTop 25%
🗺 California: #12,239 of 60,411 inventorsTop 25%
Overall (2018): #162,346 of 503,207Top 35%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10141917 Multiple mode device implementation for programmable logic devices Senani Gunaratna, Ting Yew 2018-11-27
10079054 Selective power gating of routing resource configuration memory bits for programmable logic devices Senani Gunaratna, Ting Yew, Ronald L. Cline 2018-09-18