Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9984188 | Single ended-mode to mixed-mode transformer spice circuit model for high-speed system signal integrity simulations | — | 2018-05-29 |
| 9984189 | Data clocked retimer model | — | 2018-05-29 |
| 9972566 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou | 2018-05-15 |
| 9858370 | Spice circuit model for twinaxial cable | — | 2018-01-02 |