| 10109679 |
Wordline sidewall recess for integrating planar selector device |
Yangyin Chen |
2018-10-23 |
| 10056399 |
Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same |
Xiying Costa, Daxin Mao, Dana Lee, Yao-Sheng Lee |
2018-08-21 |
| 10038092 |
Three-level ferroelectric memory cell using band alignment engineering |
Yangyin Chen |
2018-07-31 |
| 10032908 |
Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof |
Perumal Ratnam, Juan Saenz, Guangle Zhou, Abhijit Bandyopadhyay, Tanmay Kumar |
2018-07-24 |
| 10026782 |
Implementation of VMCO area switching cell to VBL architecture |
Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu |
2018-07-17 |
| 9941331 |
Device with sub-minimum pitch and method of making |
Jordan Asher Katine, Yangyin Chen |
2018-04-10 |
| 9941299 |
Three-dimensional ferroelectric memory device and method of making thereof |
Yangyin Chen |
2018-04-10 |
| 9922709 |
Memory hole bit line structures |
Perumal Ratnam, Tianhong Yan |
2018-03-20 |
| 9859337 |
Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof |
Perumal Ratnam, Abhijit Bandyopadhyay |
2018-01-02 |