Issued Patents 2018
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141071 | Predictive count fail byte (CFBYTE) for non-volatile memory | Shantanu R. Rajwade | 2018-11-27 |
| 10126967 | Sense operation flags in a memory device | Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2018-11-13 |
| 10120751 | Techniques to recover data using exclusive OR (XOR) parity information | Jawad B. Khan, Anand S. Ramalingam | 2018-11-06 |
| 10109361 | Coarse pass and fine pass multi-level NVM programming | Ali Khakifirooz, Rohit S. Shenoy, Aliasgar S. Madraswala, Donia Sebastian, Xin Guo | 2018-10-23 |
| 10102903 | Write process for a non volatile memory device | Tommaso Vali, Violante Moschiano, Andrea D'Alessandro | 2018-10-16 |
| 10043574 | Programming memories with multi-level pass signal | Shyam Sunder Raghunathan, Krishna K. Parat, Charan Srinivasan | 2018-08-07 |
| 9977622 | Buffer operations in memory | Shantanu R. Rajwade | 2018-05-22 |
| 9922704 | Programming memories with multi-level pass signal | Shyam Sunder Raghunathan, Krishna K. Parat, Charan Srinivasan | 2018-03-20 |
| 9910594 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Shantanu R. Rajwade, Toru Tanzawa | 2018-03-06 |
| 9870169 | Interleaved all-level programming of non-volatile memory | Anand S. Ramalingam, Dale Juenemann | 2018-01-16 |
| 9865357 | Performing read operations on a memory device | Deepak Thimmegowda, Aaron Yip, Shantanu R. Rajwade | 2018-01-09 |