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Systems, apparatuses, and methods for chained fused multiply add |
Jesus Corbal, Robert Valentine, Roman S. Dubtsov, Nikita A. Shustrov, Mark J. Charney +4 more |
2018-12-04 |
| 9990206 |
Mechanism for instruction set based thread execution of a plurality of instruction sequencers |
Hong Wang, John Shen, Richard Hankins, Gautham Chinya, Bryant Bigbee +9 more |
2018-06-05 |
| 9977674 |
Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction |
Jeffrey P. Rupley, II, Edward A. Brekelbaum, Bryan Black |
2018-05-22 |
| 9934155 |
Method, system, and apparatus for page sizing extension |
Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa |
2018-04-03 |
| 9934032 |
Processors, methods, and systems to implement partial register accesses with masked full register accesses |
Seyed Yahya Sotoudeh, Buford M. Guy |
2018-04-03 |
| 9898286 |
Packed finite impulse response (FIR) filter processors, methods, systems, and instructions |
Edwin Van Dalen, Martinus Cornelis Wezelenburg, Steven Roos, Moshe Maor |
2018-02-20 |
| 9875185 |
Memory sequencing with coherent and non-coherent sub-systems |
Chunhui Zhang, George Z. Chrysos, Ramacharan Sundararaman, Chung-Lun Chan, Federico Ardanaz |
2018-01-23 |
| 9875213 |
Methods, apparatus, instructions and logic to provide vector packed histogram functionality |
Galina Ryvchin, Michael Behar |
2018-01-23 |