Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10073776 | Shadow tag memory to monitor state of cachelines at different cache level | Sriram Srinivasan | 2018-09-11 |
| 9946646 | Systems and method for delayed cache utilization | — | 2018-04-17 |
| 9940247 | Concurrent access to cache dirty bits | — | 2018-04-10 |
| 9916243 | Method and apparatus for performing a bus lock and translation lookaside buffer invalidation | Paul James Moyer, Richard Martin Born, Eric Christopher Morton, David S. Christie, Marius Evers +1 more | 2018-03-13 |
| 9864681 | Dynamic multithreaded cache allocation | — | 2018-01-09 |