Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9634138 | Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout | Ukjin Roh, Shashank S. Ekbote | 2017-04-25 |
| 9543437 | Integrated circuit with dual stress liner boundary | Greg Baldwin | 2017-01-10 |